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e c 9232 multi - channel tft lcd supply e-cmos corp. (www.ecmos.com.tw) 5e26n - rev. f001 1/14 general description the EC9232 is an integrated power supply solution o ptimized for small to medium size thin-film transis tor (tft) liquid crystal displays (lcds). the boost converte r operates at the frequency of 1.2mhz. the integrat ed n channel fet has a typical current limit of 3.0a and can support output voltages up to 20v. the gate-on and gate-off charge pumps provide regulated tft-lcd gat e-on and gate-off supplies. both outputs can be adj usted by external resistive voltage-dividers. the gpm is a flicker compensation circuit to reduce the coupli ng effect of gate lines; the gate-shaping timing is controlled b y the timing-controller to modulate the gate-on vol tage, v ghm . it also can delay the gate-on voltage during power- on to achieve a correct power-on sequence for gate driver ics. both the power-on delay time and the falling t ime of the gate-on voltage are programmable by exte rnal capacitor and resistor. the integrated operational amplifier is typically used for lcd v com driving; the output can sink or source up to 350ma short-circuit current. t his operational amplifier features fast slew rate ( 40v/us), wide bandwidth (20mhz), and rail-to-rail outputs as well . a built-in voltage detector generates a reset sig nal when the input voltage drops below a specified level. the re set signal is active low, and the detecting level i s decided by an external resistor divider. the EC9232 is availab le in a thin 24-pin 4x4 mm v qfn green package. features v qfn-24 pin configuration 2.5v to 5.5v input supply current-mode boost regulator - 1.2mhz switching frequency - integrated 20v/3.0a 160m fet - fast transient response to pulsed load - high efficiency up to 90% - adjustable high-accuracy output voltage(1% ) - over current protection - over voltage protection vgh positive charge pump controller vgl negative charge pump controller integrated high performance operational amplifier - 350ma output short-circuit current - 40v/us fast slew rate - 20mhz bandwidth - rail-to-rail output low-voltage detection circuit gpm controller - adjustable falling time - adjustable delay thermal shutdown thin 4x4 mm 24-lead vqfn package applications tft lcd for notebooks tft lcd for monitors car navigation display portable equipment
e c 9232 multi - channel tft lcd supply e-cmos corp. (www.ecmos.com.tw) 5e26n - rev. f001 2/14 number name pin description 1 opa+ operational amplifier non-inverting input. 2 opa- operational amplifier inverting input. 3 opao operational amplifier output. 4 bgnd ground for operational amplifier and charge pumps. 5 avdd charge pump supply and operational amplifier supply . 6 drvp positive charge pump driving output. 7 drvn negative charge pump driving output. 8 vflk timing control pin for charging or discharging vghm . 9 rstnn voltage detector output for reset, active low. rstn n is an open-drain output. 10 fbp positive charge pump feedback sense input. 11 fbn negative charge pump feedback sense input. 12 ref reference output. all power outputs are disabled un til ref exceeds its uvlo threshold. 13 vin supply for pwm, reference and other circuits. 14 agnd analog ground. 15 vdiv voltage detector divider input. 16 comp boost converter error amplifier compensation node. 17 fb boost converter feedback voltage sense input. 18,19 pgnd boost converter power ground (source of the interna l nmos switch). 20 lx boost converter switching node (drain of the intern al nmos switch). 21 re switch input to discharge vghm. 22 vghm supply voltage for gate driver. 23 vgh input to charge vghm. 24 vdpm gpm startup delay input; charged with a constant 5 a current. - tp thermal pad, connect to agnd. pin description ordering information EC9232 nn xx x part number package marking marking information EC9232nnq1r vqfn 24l 9232 lllll 1. lllll lot no q1:vqfn r:tape & reel
e c 9232 multi - channel tft lcd supply e-cmos corp. (www.ecmos.com.tw) 5e26n - rev. f001 3/14 function block diagram
e c 9232 multi - channel tft lcd supply e-cmos corp. (www.ecmos.com.tw) 5e26n - rev. f001 4/14 typical application diagram
e c 9232 multi - channel tft lcd supply e-cmos corp. (www.ecmos.com.tw) 5e26n - rev. f001 5/14 package thermal resistance, ja power rating (t a < 25 c ) power rating (25 < t a < 85 c ) power rating (t a = 85c ) 24-ld qfn 44c /w 2.28w (125 - t a ) / 44 w 0.9w input supply voltage, vin -0.3v to 6.5v voltages on rstnn, vdiv, vflk -0.3v to 6.5v voltages on avdd, lx -0.3v to 22v voltages on vgh, vghm, re -0.3v to 38v voltages on fb, fbp, fbn, comp, ref, vdpm -0.3v to (vin+0.3v) voltages on drvp, drvn, opa+,opa-, opao -0.3v to (avdd+0.3v) storage temperature range -65c to 150c lead temperature (soldering, 10s maximum) 260c esd, human body mode 2kv esd, machine mode 200v absolute maximum ratings note1: all voltages are referenced to ground with p gnd and agnd pins grounded. note2: absolute maximum ratings indicate limits b eyond which permanent damage to the device may occur. these are stress ratings only, and funct ional operation of the device at these or any other conditions beyond those indicated under "recommende d operating conditions" is not implied. for guaranteed specifications and test conditions, see the electrical specifications. recommended operation conditions power dissipation ratings junction temperature range -40c to 125c ambient temperature range -40c to 85c
e c 9232 multi - channel tft lcd supply e-cmos corp. (www.ecmos.com.tw) 5e26n - rev. f001 6/14 electrical specifications (v in =5v, av dd = 13v, t a =25c, unless otherwise specified) parameter symbol test conditions min typ max units system supply input supply voltage v in 2.5 -- 5.5 v v in falling 2.05 2.15 2.25 v vin under voltage lockout threshol v uvlo v in rising 2.15 2.25 2.35 v v fb = 1.35v, lx no switching -- 0.6 0.9 ma vin quiescent current i q v fb = 1.15v, lx switching -- 3 4.5 ma thermal shutdown t shdn -- 160 -- main boost regulator output voltage range av dd vin - 18 v fb regulation voltage v fb fb=comp,c comp =1nf 1.238 1.25 1.262 v fb fault trip level falling edge 0.95 1 1.05 v fb load regulation 0< i load < full, transient only -1 % fb line regulation v in = 2.5 to 5.5v 0.05 0.15 %/v fb input bias current v fb = 1.25v -40 0 40 na fb transconductance g m ? i=5ua at comp, fb = comp 85 ua/v fb voltage gain a v fb to comp 1500 v/v lx current limit v fb =1.1v, duty cycle = 75% 2.5 3 3.5 a lx on-resistance r ds_lx i lx = 200ma 0.16 lx leakage current v lx = 19v, t a = +25c 0.01 20 ua current-sense transresistance 0.1 0.2 0.3 v/a soft-start period t ss1 14 ms reference ref output voltage v ref i ref =50ua 1.238 1.25 1.262 v v ref falling 0.86 ref under voltage lockout threshold v ref_uvlo v ref rising 1.08 ref load regulation i ref 0 e c 9232 multi - channel tft lcd supply e-cmos corp. (www.ecmos.com.tw) 5e26n - rev. f001 7/14 positive charge-pump regulator avdd supply range v avdd 6 18 v operating frequency f osc_cp 500 600 700 khz fbp regulation voltage v fbp 1.23 1.25 1.27 v fbp input bias current i fbp_bias v fbp =1.5v, t a = +25c -40 - 40 na drvp p-ch on-resistance r drvpp 3 6 drvp n-ch on-resistance r drvpn 3 6 fbp fault trip level falling edge 0.95 1 1.05 v soft-start period t ss2 3.4 ms negative charge-pump regulator avdd supply range v avdd 6 18 v operating frequency f osc_cp 500 600 700 khz fbn regulation voltage v fbn 235 250 265 mv fbn input bias current i fbn_bias v fbn = 0v, t a = +25c -40 - 40 na drvn p-ch on-resistance r drvnp 3 6 drvn n-ch on-resistance r drvnn 3 6 fbn fault trip level rising edge 0.4 0.45 0.5 v soft-start period t ss3 3.4 ms operational amplifier avdd supply range v avdd 6 18 v v avdd overvoltage threshold v ovp 19 20 21 v avdd under voltage lockout threshold v avdd_uvlo 3.8 4 4.2 v avdd supply current i avdd buffer configuration, v opa+ =v avdd /2,no load 2 ma input offset voltage v os v opa-, v opa+ =v avdd /2, t a = +25c 2 15 mv input bias current i bias v opa-, v opa+ =v avdd /2, t a = +25c -40 40 na input common-mode voltage range 0 vavdd v output-voltage-swing high voh buffer configuration, opao i out =25 ma v avdd - 350 mv output-voltage-swing low vol buffer configuration, opao i out = -25 a 350 mv slew rate sr v out 20% to 80% with cl=10pf, rl=10k 40 v/us -3db bandwidth bw cl=10pf, rl=10k 40 mhz v opa+ =v avdd /2 , short output to bgnd (sourcing) 350 ma short-circuit current iscc v opa+ =v avdd /2 , short output to avdd (sinking) 350 ma
e c 9232 multi - channel tft lcd supply e-cmos corp. (www.ecmos.com.tw) 5e26n - rev. f001 8/14 application information the EC9232 offers an all-in-one solution for tft lc d. the chip includes a high-efficiency boost conver ter with a 20v/3a on-chip n-channel transistor for biasing of the lcd, a regulated positive charge pump, a regula ted negative charge pump, a vcom buffer and a gate puls e modulation circuit. a voltage detector circuit ge nerates a reset signal when the input voltage falls below t he preset threshold. tft lcd boost converter (avdd) the lcd panel avdd supply is generated from a high- efficiency pwm boost converter operating with curre nt mode control, and the switching frequency is 1.2mhz . during the on-period, ton, the synchronous fet connects one end of the inductor to ground, therefo re increasing the inductor current. after the fet t urns off, the inductor switching node, lx, is charged to a positi ve voltage by the inductor current. the freewheelin g diode turns on and the inductor current flows to the outp ut capacitor. the converter operates in the continu ous conduction mode (ccm) when the average input curren t iin is at least one-half of the inductor peak- to -peak ripple current, i lpp . settling time tsetling buffer configuration, v opa+ =5.5v to7.5v,with no output loading 220 ns reset control falling edge at vin=5v 1.225 1.25 1.275 vdiv threshold v div falling edge at vin=1.8v 1.213 1.25 1.287 v vdiv input current ta=+2 5 -40 0 40 na vdiv hysteresis v div 50 mv rstnn output voltage v rst i sink = 1ma 0.2 v reset blanking time t blk 163 ms gpm control vgh input voltage range v vgh 36 v vdpm=1.5v,vflk=high 600 vgh input current i vgh vdpm=1.5v,vflk=low 300 ua vflk input low voltage v il 0.6 v vflk input high voltage v ih 2 v vflk input current vflk input current -40 40 na propagation delay of vflk to vghm rising tdelay vgh=25v 100 ns vgh to vghm switch on resistance rds_high vdm=1.5v,vflk=high 15 30 re to vgm switch on resistance rds_low vdm=1.5v,vflk=low 30 60 vghm-to Cgnd pull-down resistance r vghm vdpm=0v 2.5 k
e c 9232 multi - channel tft lcd supply e-cmos corp. (www.ecmos.com.tw) 5e26n - rev. f001 9/14 the output voltage, avdd, is determined by the duty cycle, d, of the power fet on-time and the input v oltage, v in . the average load current, i load , can be calculated from the power conservation law . h v in i in = avdd i load where is the power conversion efficiency. for a lower lo ad current, the inductor current would decay to zer o during the free- wheeling period and the output node would be discon nected from the inductor for the remaining portion of the switching period. the converter would operate in the disconti nuous conduction mode (dcm). current mode control i s well known for its robustness and fast transient response. an inner cur rent feedback loop sets the on-time and the duty cy cle such that the current through the inductor equals to the current computed by the compensator. this loop acts within one switching cycle. a slope compensation ramp is added to suppress sub-ha rmonic oscillations. an outer voltage feedback loop subtracts the voltage on the fb pin from the internal reference vo ltage and feeds the difference to the compensator o perational transconductance (gm) amplifier. this amplifier is compensated by an external r-c network to allow the user to optimize the transient response and loop stability for the speci fic application conditions. compensator selection this current mode boost converter has a current sen se loop and a voltage feedback loop. the current se nse loop does not need any compensation. the voltage fe edback loop is compensated by an external series r- c network r comp and c comp from comp pin to ground. r comp sets the high-frequency loop gain and the unity gain bandwidth of the loop which determines t he transient response. c comp together with r comp determine the phase margin which relates to loop stability. users can adjust r comp and c comp by the following equations to reach fast transient response and better regulation. for example, when v in =5v, v boost =13.2v, c out =40uf, l boost =10uh, i boost =1a, we put 84.5k for r comp and 820pf for c comp in typical application diagram.
e c 9232 multi - channel tft lcd supply e-cmos corp. (www.ecmos.com.tw) 5e26n - rev. f001 10/14 output capacitor selection the output voltage ripple due to converter switchin g is determined by the output capacitor total capac itance, c out , and the output capacitor total effective series r esistance, esr. the first ripple component can be reduced by increa sing c out since fosc is fixed 1.2mhz(typical). changing c out may require adjustment of compensation r and c in order to provide adequate phase margin and loop bandwidth. the second ripple component can be reduced by selecting low-esr ceramic capacitors and using several smaller capacitors in parallel in stead of just one large capacitor. inductor selection to prevent magnetic saturation of the inductor core the inductor has to be rated for a maximum current larger than i pk in a given application. since the chip provides cu rrent limit protection of 3a (typ) it is generally recommended that the inductor be rated at least for 3a. selection of the inductor requires trade-off betwee n the physical size (footprint x height) and its el ectrical properties (current rating, inductance, resistance) . within a given footprint and height, an inductor with larger inductance typically comes with lower current ratin g and often larger series resistance. larger induct ance typically requires more turns on the winding, a sma ller core gap or a core material with a larger rela tive permeability. an inductor with a larger physical si ze has better electrical properties than a smaller inductor. it is desirable to reduce the ripple current i lpp in order to reduce voltage noise on the input and output capacitors. in practice, the inductor is often much larger than the capacitors and it is easier and cheaper to inc rease the size of the capacitors. the ripple current i lpp is then chosen the largest possible while at the s ame time not degrading the maximum input and output current that the converter can operate with before reaching the current limit of the chip or the rated current of the induc tor. for example, i lpp could be set to 20% of i max . voltage detector circuit during power-up, once v in exceeds v uvlo (2.25v typical), the controller initiates a 163ms blanking period during which the input voltage at v div is ignored and the rstnn pin is floated to high im pedance. an external pull up resistor should pull rstnn high. after this blankin g period, the v div function is enabled, with rstnn driven low if v div falls below v div , or floated high if v div rises above v div .to the external voltage vext, the rising and falli ng detection thresholds v det ,high and v det ,low, respectively are set by the external voltage divider r3, r4.
e c 9232 multi - channel tft lcd supply e-cmos corp. (www.ecmos.com.tw) 5e26n - rev. f001 11/14 positive charge pump (vgh) the positive charge pump is used to generate the tf t lcd gate on voltage. the output voltage, vgh, can be set by an external resistive divider. voltage vfbp is typically 1.25v. a single stage charge pump can produce an output voltage less than approximately twice the ch arge pump input voltage avdd. the maximum voltage v gh should not exceed 36v if it is used to supply the g pm circuit. the output voltage vgh is regulated as the following equation. negative charge pump (vgl) the negative charge pump is used to generate the tf t lcd gate off voltage. the output voltage, vgl, is set with an external resistive divider from its output to ref with the midpoint connected to fbn. the erro r amplifier compares the feedback signal from fbn with an inter nal reference 250mv. the output voltage vgl is regu lated as the following equation.
e c 9232 multi - channel tft lcd supply e-cmos corp. (www.ecmos.com.tw) 5e26n - rev. f001 12/14 gate-pulse modulator (gpm) the gpm is a flicker compensation circuit to reduce the coupling effect of gate lines, and is controll ed by timing controller to modulate vghm, the gate-on voltage. t his block is not activated until the below 3 condit ions are satisfied: 1) the input voltage exceeds its uvlo, 2) no fault condition is detected, and 3) v dpm exceeds its turn-on threshold. once gpm activates and v flk is high, the internal switch between v gh and v ghm turns on and the switch between v ghm and re turns off. if v flk is low, the internal switch between v gh and v ghm turns off and the switch between v ghm and re turns on. at that time, the falling time and delay time of the gate-on volt age are programmable by an external resistor connec ted between re and gnd. operational amplifier the operational amplifier is typically used for lcd v com buffer. the v com buffer generates the bias supply for the back plane of an lcd screen which is capacitively c oupled to the pixel drive voltage. the purpose of t he v com buffer is to hold the bias voltage steady while pix el voltage changes dynamically. the buffer is desig ned to sustain up to 350ma of output short-circuit curren t. in transients, it can deliver up to 350ma at whi ch point the over current protection circuit limits the output c urrent. excessive current draw over a period of tim e may cause the chip temperature to rise and set off the over t emperature protection circuit. soft-start function the ic employs a internal soft-start function to mi nimize inrush current and voltage overshoot, and en sure a well-defined startup behaviour. the soft-start time of the boost controller is 14ms (typ), and the sof t-start time of positive and negative charge pump is 3.4ms (typ). under voltage protection during steady-state operation, if the feedback volt age pin fb is below 1v of the nominal value, the ec 9232 activates an internal fault timer. if any condition indicates a continuous fault for the fault timer d uration (55ms typ), the ic sets the fault latch to shut down all its outputs except the reference. once the fault co ndition is removed, cycle the vin (below the uvlo falling thre shold) to clear the fault latch and reactivate the device. the fault-detection circuit is disabled during the soft-start ramp. the positive and negative charge pump controller al so provide the under voltage protection function du ring steady-state operation. if f bp voltage is lower than 1v (typ) or f bn voltage is higher than 0.45v (typ), and the fault duration is over 55ms (typ), the ic sets the fault latch to shut down all its outputs as well. thermal-overload protection the EC9232 provides a thermal-overload protection t o prevents excessive power dissipation from overhea ting the ic. when the junction temperature exceeds tj = 160c, a thermal sensor activates the fault protect ion, which shuts down all outputs except the reference. to resume normal function, the temperature must coo l down by 15c and cycle the ic power to clear the fault l atch.
e c 9232 multi - channel tft lcd supply e-cmos corp. (www.ecmos.com.tw) 5e26n - rev. f001 13/14 startup sequence power-off sequence
e c 9232 multi - channel tft lcd supply e-cmos corp. (www.ecmos.com.tw) 5e26n - rev. f001 14/14

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